#if defined(ARCTIC)
/**
 @file sys_at_qos.c

 @date 2020-8-29

 @version v1.0

 The file contains AT QoS APIs of sys layer
*/

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_error.h"
#include "ctc_debug.h"
#include "sys_usw_common.h"
#include "sys_usw_chip.h"
#include "sys_usw_qos.h"
#include "sys_at_qos.h"
#include "sys_usw_dma.h"
#include "sys_usw_stats_api.h"
#include "drv_api.h"
#include "sys_at_datapath.h"

extern sys_queue_master_t* p_usw_queue_master[CTC_MAX_LOCAL_CHIP_NUM_PP];

extern int32
sys_usw_qos_get_fast_ecn(uint8 lchip, uint32* value);
extern int32
sys_usw_qos_set_fast_ecn(uint8 lchip, uint32 value);
extern int32
_sys_at_qos_queue_map_port_fixed_mode(uint8 lchip, sys_port_info_t* port_info, ctc_qos_queue_map_t* que_map);

STATIC int32
_sys_at_qos_dump_status(uint8 lchip)
{
    sys_usw_qos_policer_dump_status(lchip);
    sys_at_qos_queue_dump_status(lchip);
    sys_usw_qos_sched_dump_status(lchip);

    sys_at_qos_drop_dump_status(lchip);

    return CTC_E_NONE;
}

int32
sys_at_qos_set_port_dynamic_switch(uint8 lchip, uint16 lport, uint8 index)
{
    sys_port_info_t port_info;

    sal_memset(&port_info, 0, sizeof(sys_port_info_t));

    CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, index, &port_info));
    CTC_ERROR_RETURN(sys_at_sch_set_wrr_en(lchip, &port_info, 0));
    CTC_ERROR_RETURN(_sys_at_qos_queue_map_port_fixed_mode(lchip, &port_info, NULL));

    return CTC_E_NONE;
}

#define ______SYS_AT_QOS_API______

int32
sys_at_get_channel_by_port(uint8 lchip, uint32 gport, uint16 *channel)
{
    uint16 lport = 0;
    uint32 cmd = 0;
    DsIpeFwdDestPortMap_m ipefwd_portmap;

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);

    cmd = DRV_IOR(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ipefwd_portmap));
    *channel = GetDsIpeFwdDestPortMap(V, ppDestPort_f, &ipefwd_portmap);

    return CTC_E_NONE;
}

int32
sys_at_get_channel_by_sub_channel(uint8 lchip, uint8 dp_id, uint8 sub_chan, uint16 *chan)
{
    uint32 cmd = 0;
    EpeHeaderAdjustChannelPortMap_m ChannelPortMap;

    cmd = DRV_IOR(EpeHeaderAdjustChannelPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, sub_chan & 0x1F, DRV_CMD_PP_EN(cmd), &ChannelPortMap));
    *chan = GetEpeHeaderAdjustChannelPortMap(V, g_0_ppDestPort_f + (dp_id & 0x1), &ChannelPortMap);
    return CTC_E_NONE;
}

int32
sys_at_get_sub_channel_by_channel(uint8 lchip, uint16 chan, uint16 *sub_chan)
{
    uint32 cmd = 0;
    UcQWritePortChannelMap_m uc_chan_map;

    cmd = DRV_IOR(UcQWritePortChannelMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(SYS_PP_BASE(lchip), chan, cmd, &uc_chan_map));
    *sub_chan = GetUcQWritePortChannelMap(V, g_0_channelId_f, &uc_chan_map);

    return CTC_E_NONE;
}

int32
sys_at_add_port_to_channel(uint8 lchip, uint32 lport, uint16 channel, uint8 is_pp)
{
    uint32 cmd = 0;
    DsIpeFwdDestPortMap_m ipefwd_portmap;
    DsMcQWriteDestPortMap_m mcq_portmap;

    sal_memset(&ipefwd_portmap, 0, sizeof(ipefwd_portmap));
    sal_memset(&mcq_portmap, 0, sizeof(mcq_portmap));
    /*add lport to ppport*/
    if (is_pp)
    {
        SetDsIpeFwdDestPortMap(V, ppDestPort_f, &ipefwd_portmap, channel);
        cmd = DRV_IOW(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, DRV_CMD_PP_EN(cmd), &ipefwd_portmap));

        SetDsMcQWriteDestPortMap(V, ppDestPort_f, &mcq_portmap, channel);
        cmd = DRV_IOW(DsMcQWriteDestPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, DRV_CMD_PP_EN(cmd), &mcq_portmap));
    }
    else
    {
        SetDsIpeFwdDestPortMap(V, ppDestPort_f, &ipefwd_portmap, channel);
        cmd = DRV_IOW(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ipefwd_portmap));

        SetDsMcQWriteDestPortMap(V, ppDestPort_f, &mcq_portmap, channel);
        cmd = DRV_IOW(DsMcQWriteDestPortMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &mcq_portmap));
    }
    return CTC_E_NONE;
}
int32
sys_at_remove_port_from_channel(uint8 lchip, uint32 lport, uint16 channel)
{
    uint32 cmd = 0;
    DsIpeFwdDestPortMap_m ipefwd_portmap;
    DsMcQWriteDestPortMap_m mcq_portmap;

    sal_memset(&ipefwd_portmap, 0, sizeof(ipefwd_portmap));
    sal_memset(&mcq_portmap, 0, sizeof(mcq_portmap));
    if (!SYS_IS_NETWORK_CHANNEL(channel))
    {
        channel = MCHIP_CAP(SYS_CAP_CHANID_DROP);
    }

    /*add lport to ppport*/
    SetDsIpeFwdDestPortMap(V, ppDestPort_f, &ipefwd_portmap, channel);
    cmd = DRV_IOW(DsIpeFwdDestPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &ipefwd_portmap));

    SetDsMcQWriteDestPortMap(V, ppDestPort_f, &mcq_portmap, channel);
    cmd = DRV_IOW(DsMcQWriteDestPortMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, lport, cmd, &mcq_portmap));

    return CTC_E_NONE;
}

STATIC int32
_sys_at_qos_monitor_drop_add_to_asic(uint8 lchip, ctc_qos_queue_drop_monitor_t* drop_monitor, uint16 src_chan, uint16 dst_chan, uint8 is_cpu_port, uint16 sub_queue_id)
{
    BufferStoreSpanOnDropCtl_m uc_span_ctl;
    McQWriteSpanOnDropCtl_m mc_span_ctl;
    uint32 chan_en_uc = 0;
    uint32 chan_en_mc = 0;
    uint32 cmd        = 0;
    uint16 pp_bmp     = 0;
    uint8 core_pp_num = SYS_CORE_PP_NUM(lchip) ;
    uint8 src_pp_id   = SYS_PP_BY_SUB_CHAN(src_chan);
    uint8 src_dp_id   = SYS_DP_BY_SUB_CHAN(src_chan);
    uint8 src_dp_chan = SYS_DP_CHAN_BY_SUB_CHAN(src_chan);
    uint8 dst_pp_id   = SYS_PP_BY_SUB_CHAN(dst_chan);
    uint8 dst_dp_id   = SYS_DP_BY_SUB_CHAN(dst_chan);
    uint8 dst_dp_chan = SYS_DP_CHAN_BY_SUB_CHAN(dst_chan);
    uint8 bmp         = (lchip - SYS_PP_BASE(lchip) >= core_pp_num) ? 0x83 : 0x43;
    uint8 enable      = (0xff == sub_queue_id) ? 0 : 1;
    uint8 index       = 0;
    uint8 step_uc     = 0;
    uint8 step_mc     = 0;

    sal_memset(&uc_span_ctl, 0, sizeof(uc_span_ctl));
    sal_memset(&mc_span_ctl, 0, sizeof(mc_span_ctl));

    for (index = 0; index < core_pp_num; index++)
    {
        CTC_BIT_SET(pp_bmp, index);
    }
    bmp |= pp_bmp << 2;

    /*uc*/
    cmd = DRV_IOR(BufferStoreSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &uc_span_ctl));
    step_uc = BufferStoreSpanOnDropCtl_g_1_spanOnDropChannelEn_f - BufferStoreSpanOnDropCtl_g_0_spanOnDropChannelEn_f;
    chan_en_uc = GetBufferStoreSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + ((src_pp_id << 1) | src_dp_id) * step_uc, &uc_span_ctl);

    /*mc*/
    cmd = DRV_IOR(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &mc_span_ctl));
    step_mc = McQWriteSpanOnDropCtl_g_1_spanOnDropChannelEn_f - McQWriteSpanOnDropCtl_g_0_spanOnDropChannelEn_f;
    chan_en_mc = GetMcQWriteSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + ((src_pp_id << 1) | src_dp_id) * step_mc, &mc_span_ctl);

    if (enable)
    {
        /*uc*/
        CTC_BIT_SET(chan_en_uc, src_dp_chan);
        SetBufferStoreSpanOnDropCtl(V, spanOnDropEn_f, &uc_span_ctl, 1);
        SetBufferStoreSpanOnDropCtl(V, spanOnDropMode_f, &uc_span_ctl, 3);
        SetBufferStoreSpanOnDropCtl(V, spanOnDropRandomEn_f, &uc_span_ctl, 1);
        SetBufferStoreSpanOnDropCtl(V, spanOnDropRandomThreshold_f, &uc_span_ctl, 1 << (15 - drop_monitor->rate));
        SetBufferStoreSpanOnDropCtl(V, spanOnDropTrafficClass_f, &uc_span_ctl, drop_monitor->pri_class_bmp ? drop_monitor->pri_class_bmp : 0xFF);

        /*mc,must set dest channel and queue first, bug122952*/
        SetMcQWriteSpanOnDropCtl(V, sodDest_channelId_f, &mc_span_ctl, dst_dp_chan);
        SetMcQWriteSpanOnDropCtl(V, sodDest_dpId_f, &mc_span_ctl, dst_dp_id);
        SetMcQWriteSpanOnDropCtl(V, sodDest_ppId_f, &mc_span_ctl, dst_pp_id);
        SetMcQWriteSpanOnDropCtl(V, sodDest_queueOffset_f, &mc_span_ctl, sub_queue_id);
        cmd = DRV_IOW(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &mc_span_ctl));

        CTC_BIT_SET(chan_en_mc, src_dp_chan);
        SetMcQWriteSpanOnDropCtl(V, spanOnDropEn_f, &mc_span_ctl, is_cpu_port ? 0 : 1);
        SetMcQWriteSpanOnDropCtl(V, spanOnDropRandomEn_f, &mc_span_ctl, 1);
        SetMcQWriteSpanOnDropCtl(V, spanOnDropMode_f, &mc_span_ctl, 3);
        SetMcQWriteSpanOnDropCtl(V, spanOnDropRandomThreshold_f, &mc_span_ctl, 1 << (15 - drop_monitor->rate));
        SetMcQWriteSpanOnDropCtl(V, spanOnDropTrafficClass_f, &mc_span_ctl, drop_monitor->pri_class_bmp ? drop_monitor->pri_class_bmp : 0xFF);
    }
    else
    {
        CTC_BIT_UNSET(chan_en_uc, src_dp_chan);
        CTC_BIT_UNSET(chan_en_mc, src_dp_chan);
    }
    SetBufferStoreSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + ((src_pp_id << 1) | src_dp_id) * step_uc, &uc_span_ctl, chan_en_uc);
    SetMcQWriteSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + ((src_pp_id << 1) | src_dp_id) * step_mc, &mc_span_ctl, chan_en_mc);

    cmd = DRV_IOW(BufferStoreSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL_BMP(lchip, 0, (((uint64)bmp << 32) | cmd), &uc_span_ctl));

    cmd = DRV_IOW(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &mc_span_ctl));

    return CTC_E_NONE;
}

int32
sys_at_qos_set_monitor_drop_queue_id(uint8 lchip,  ctc_qos_queue_drop_monitor_t* drop_monitor, sys_nh_info_dsnh_t* p_nhinfo)
{
    uint32 cmd = 0;
    BufferStoreSpanOnDropCtl_m uc_span_ctl;
    McQWriteSpanOnDropCtl_m mc_span_ctl;
    EpeHdrAdjSpanCtl_m hdradj_span_ctl;
    EpeHdrAdjExcp_m epe_exp;
    DsMetFifoExcp_m met_exp;
    uint8 step = 0;
    uint8 gchip = 0;
    uint8 discard_en = 0;
    uint16 lport = 0;
    uint16 dst_lport = 0xffff;
    uint32 dst_dp_chan = 0;
    uint32 dst_pp_id = 0;
    uint32 dst_dp_id = 0;
    uint32 src_gport = 0;
    uint32 dst_gport = 0;
    uint8 is_cpu_port = 0;
    uint16 sub_queue_id = 0;
    uint32 field_val = 0;
    uint32 nexthop_ptr = 0;
    uint16 index = 0;
    uint32 src_pp_id = 0;
    uint32 src_dp_id = 0;
    uint32 src_dp_chan = 0;
    uint32 dest_map = 0;
    sys_port_info_t port_info;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
    if (drop_monitor->enable)
    {
        CTC_MAX_VALUE_CHECK(drop_monitor->rate, 15);
    }
    lchip = SYS_PP_BASE(lchip);
    src_gport = drop_monitor->src_gport;
    dst_gport = drop_monitor->nhid ? p_nhinfo->gport : drop_monitor->dst_gport;
    nexthop_ptr = p_nhinfo->dsnh_offset;
    if(src_gport == dst_gport)
    {
        return CTC_E_INVALID_PARAM;
    }
    if (CTC_IS_CPU_PORT(dst_gport))
    {
        is_cpu_port = 1; /*mc mod to cpu not support*/
        dst_dp_chan = SYS_DMA_SUB_CHAN;
        nexthop_ptr = CTC_PKT_CPU_REASON_QUEUE_DROP_PKT << 4;
        dest_map = SYS_ENCODE_EXCP_DESTMAP(gchip, p_nhinfo->ecmp_group_id);/*temp reuse as sub queue id*/
    }
    else if(drop_monitor->nhid && p_nhinfo->nh_entry_type == SYS_NH_TYPE_ILOOP)
    {
        dst_dp_chan = SYS_LOOP_SUB_CHAN;
        dest_map = SYS_ENCODE_DESTMAP(gchip, SYS_RSV_PORT_ILOOP_ID);
    }
    else if(drop_monitor->nhid && p_nhinfo->nh_entry_type == SYS_NH_TYPE_ELOOP)
    {
        dst_dp_chan = SYS_LOOP_SUB_CHAN;
        dest_map = SYS_ENCODE_DESTMAP(gchip, SYS_RSV_PORT_ELOOP_ID);
    }
    else
    {
        uint8 mcq_ofst = 0;
        sal_memset(&port_info, 0 ,sizeof(sys_port_info_t));
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(dst_gport, lchip, dst_lport);
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, dst_lport, CTC_MAP_GPORT_TO_MCHAN_IDX(dst_gport), &port_info));
        if (!SYS_IS_NETWORK_CHANNEL(port_info.chan_id))
        {
            SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
            return CTC_E_INVALID_PORT;
        }
        CTC_ERROR_RETURN(sys_at_queue_get_span_on_drop_mcq(lchip, &port_info, &mcq_ofst));
        sub_queue_id = mcq_ofst;
        dst_dp_chan = port_info.sub_chan_id;
        dst_pp_id = port_info.pp_id;
        dst_dp_id = port_info.dp_id;
        dest_map = SYS_ENCODE_DESTMAP(gchip, dst_lport);
    }

    sal_memset(&port_info, 0 ,sizeof(sys_port_info_t));
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(src_gport, lchip, lport);
    CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, CTC_MAP_GPORT_TO_MCHAN_IDX(src_gport), &port_info));

    if (!SYS_IS_NETWORK_CHANNEL(port_info.chan_id))
    {
        SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }
    src_dp_chan = port_info.sub_chan_id;
    src_pp_id = port_info.pp_id;
    src_dp_id = port_info.dp_id;

    cmd = DRV_IOR(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mc_span_ctl));


    if (GetMcQWriteSpanOnDropCtl(V, spanOnDropRandomEn_f, &mc_span_ctl))
    {
        if(dst_dp_chan != GetMcQWriteSpanOnDropCtl(V, sodDest_channelId_f, &mc_span_ctl)
           || dst_pp_id != GetMcQWriteSpanOnDropCtl(V, sodDest_ppId_f, &mc_span_ctl)
           || dst_dp_id != GetMcQWriteSpanOnDropCtl(V, sodDest_dpId_f, &mc_span_ctl))
        {
            SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Can Not Bind Different Destport. \n");
            return CTC_E_INVALID_PORT;
        }
    }

    if (drop_monitor->enable)
    {
        /*epe match*/
        cmd = DRV_IOR(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl))
        discard_en = GetEpeHdrAdjSpanCtl(V, spanOnDropDiscardEn_f, &hdradj_span_ctl);
        if (dst_lport == MCHIP_CAP(SYS_CAP_RSV_PORT_MOD_ID) && !discard_en)
        {
            SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Drop Dst Port is MOD Port need enable Queue_Drop_En(ipfix)\n");
            return CTC_E_INVALID_CONFIG;
        }
        p_usw_queue_master[lchip]->monitor_drop_en = 1;

        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_QOS, SYS_WB_APPID_QOS_SUBID_QUEUE_MASTER, 1);

        SetEpeHdrAdjSpanCtl(V, spanOnDropEn_f, &hdradj_span_ctl, 1);
        SetEpeHdrAdjSpanCtl(V, spanOnDropDpInfoMapEn_f, &hdradj_span_ctl, 0x7FFF);
        /*spanOnDropDpInfoMap[11:0]{ bufsel[1bit], dpId[1bit], subChan[5bit], queueOffset[4bit]}*/
        field_val = (1 << 10) | (dst_dp_id << 9) | (dst_dp_chan & 0x1F) << 4 | (sub_queue_id);
        SetEpeHdrAdjSpanCtl(V, spanOnDropDpInfoMap_f, &hdradj_span_ctl, field_val);
        SetEpeHdrAdjSpanCtl(V, spanOnDropOffsetReset_f, &hdradj_span_ctl, 0);
        SetEpeHdrAdjSpanCtl(V, spanOnDropTypeReset_f, &hdradj_span_ctl, 1);
        SetEpeHdrAdjSpanCtl(V, spanOnDropNextHopPtr_f, &hdradj_span_ctl, nexthop_ptr);
        cmd = DRV_IOW(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl));

        /*uc Excp*/
        cmd = DRV_IOR(DsMetFifoExcp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &met_exp));
        SetDsMetFifoExcp(V, destMap_f, &met_exp, dest_map);
        SetDsMetFifoExcp(V, isSpanPkt_f, &met_exp, 1);
        cmd = DRV_IOW(DsMetFifoExcp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &met_exp));

        cmd = DRV_IOR(EpeHdrAdjExcp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &epe_exp));
        SetEpeHdrAdjExcp(V, destMap_f, &epe_exp, dest_map);
        SetEpeHdrAdjExcp(V, nextHopPtr_f, &epe_exp, nexthop_ptr);
        SetEpeHdrAdjExcp(V, isSpanPkt_f, &epe_exp, !discard_en);
        cmd = DRV_IOW(EpeHdrAdjExcp_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &epe_exp));

        CTC_ERROR_RETURN(_sys_at_qos_monitor_drop_add_to_asic(lchip, drop_monitor, 
                                                                SYS_AT_QOS_ENCOD_SUB_CHAN(src_pp_id, src_dp_id, src_dp_chan), 
                                                                SYS_AT_QOS_ENCOD_SUB_CHAN(dst_pp_id, dst_dp_id, dst_dp_chan), 
                                                                is_cpu_port, sub_queue_id));

        if (SYS_VCHIP_DUAL_CORE_MODE(lchip))
        {
            uint8 _dual_core_lchip = 0;
            uint8 _dual_src_pp_id = 0;
            uint8 _dual_dst_pp_id = 0;
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, _dual_core_lchip);
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(src_pp_id, _dual_src_pp_id);
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(dst_pp_id, _dual_dst_pp_id);
            CTC_ERROR_RETURN(_sys_at_qos_monitor_drop_add_to_asic(_dual_core_lchip, drop_monitor, 
                                                                    SYS_AT_QOS_ENCOD_SUB_CHAN(_dual_src_pp_id, src_dp_id, src_dp_chan), 
                                                                    SYS_AT_QOS_ENCOD_SUB_CHAN(_dual_dst_pp_id, dst_dp_id, dst_dp_chan), 
                                                                    is_cpu_port, sub_queue_id));
        }
    }
    else
    {
        /*1.delete span src*/
        CTC_ERROR_RETURN(_sys_at_qos_monitor_drop_add_to_asic(lchip, drop_monitor, 
                                                                SYS_AT_QOS_ENCOD_SUB_CHAN(src_pp_id, src_dp_id, src_dp_chan), 
                                                                SYS_AT_QOS_ENCOD_SUB_CHAN(dst_pp_id, dst_dp_id, dst_dp_chan), 
                                                                is_cpu_port, 0xff));
        if (SYS_VCHIP_DUAL_CORE_MODE(lchip))
        {
            uint8 _dual_core_lchip = 0;
            uint8 _dual_src_pp_id = 0;
            uint8 _dual_dst_pp_id = 0;
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(lchip, _dual_core_lchip);
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(src_pp_id, _dual_src_pp_id);
            SYS_VCHIP_DUAL_CORE_LCHIP_MAP(dst_pp_id, _dual_dst_pp_id);
            CTC_ERROR_RETURN(_sys_at_qos_monitor_drop_add_to_asic(_dual_core_lchip, drop_monitor, 
                                                                    SYS_AT_QOS_ENCOD_SUB_CHAN(_dual_src_pp_id, src_dp_id, src_dp_chan), 
                                                                    SYS_AT_QOS_ENCOD_SUB_CHAN(_dual_dst_pp_id, dst_dp_id, dst_dp_chan), 
                                                                    is_cpu_port, 0xff));
        }

        step = BufferStoreSpanOnDropCtl_g_1_spanOnDropChannelEn_f - BufferStoreSpanOnDropCtl_g_0_spanOnDropChannelEn_f;
        cmd = DRV_IOR(BufferStoreSpanOnDropCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &uc_span_ctl));
        for (index = 0; index < 16; index++)
        {
            if (GetBufferStoreSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + index * step, &uc_span_ctl))
            {
                SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Still have some port enable monitor on drop\n");
                return CTC_E_NONE;
            }
        }

        /*2.delete span dest ,if spanCnt is not 0 can not delete span dest*/
        cmd = DRV_IOR(DsErmMiscCntMc_t, DsErmMiscCntMc_g_0_spanCnt_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &field_val));
        while (field_val)
        {
            sal_task_sleep(20);
            if ((index++) > 1000)
            {
                return CTC_E_INVALID_PARAM;
            }
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &field_val));
        }
        if(is_cpu_port)
        {
            sys_usw_qos_free_monitor_drop_reason_queue_id(lchip);
        }
        p_usw_queue_master[lchip]->monitor_drop_en = 0;
        SYS_USW_REGISTER_WB_SYNC_EN(lchip, CTC_FEATURE_QOS, SYS_WB_APPID_QOS_SUBID_QUEUE_MASTER, 1);

        sal_memset(&mc_span_ctl, 0, sizeof(mc_span_ctl));
        sal_memset(&uc_span_ctl, 0, sizeof(uc_span_ctl));
        SetMcQWriteSpanOnDropCtl(V, sodDest_channelId_f, &mc_span_ctl, 63);
        cmd = DRV_IOW(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mc_span_ctl));
        cmd = DRV_IOW(BufferStoreSpanOnDropCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &uc_span_ctl));

        cmd = DRV_IOR(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl));
        SetEpeHdrAdjSpanCtl(V, spanOnDropEn_f , &hdradj_span_ctl, 0);
        SetEpeHdrAdjSpanCtl(V, spanOnDropDpInfoMapEn_f , &hdradj_span_ctl, 0);
        SetEpeHdrAdjSpanCtl(V, spanOnDropDpInfoMap_f, &hdradj_span_ctl, 0);
        SetEpeHdrAdjSpanCtl(V, spanOnDropNextHopPtr_f, &hdradj_span_ctl, 0);
        cmd = DRV_IOW(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + dst_pp_id, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl));
    }

    return CTC_E_NONE;
}

int32
sys_at_qos_get_monitor_drop_queue_id(uint8 lchip,  ctc_qos_queue_drop_monitor_t* drop_monitor)
{
    uint32 cmd = 0;
    uint32 dst_chan_id = 0;
    uint32 src_gport = 0;
    uint16 lport = 0;
    uint8 gchip = 0;
    uint32 src_pp_id = 0;
    uint32 src_dp_id = 0;
    uint32 src_dp_chan = 0;
    uint8 dst_pp_id = 0;
    uint8 dst_dp_id = 0;
    uint16 dst_dp_chan = 0;
    uint8 index = 0;
    uint8 step = 0;
    uint32 dst_chan_val = 0;
    uint32 field_val = 0;
    McQWriteSpanOnDropCtl_m mc_span_ctl;
    sys_port_info_t port_info = {0};
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    lchip = SYS_PP_BASE(lchip);
    src_gport = drop_monitor->src_gport;
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(src_gport, lchip, lport);

    CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, CTC_MAP_GPORT_TO_MCHAN_IDX(src_gport), &port_info));
    if (!SYS_IS_NETWORK_CHANNEL(port_info.chan_id))
    {
        SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Invalid localphy port \n");
        return CTC_E_INVALID_PORT;
    }
    src_dp_chan = port_info.sub_chan_id;
    src_pp_id = port_info.pp_id;
    src_dp_id = port_info.dp_id;

    cmd = DRV_IOR(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mc_span_ctl));
    step = McQWriteSpanOnDropCtl_g_1_spanOnDropChannelEn_f - McQWriteSpanOnDropCtl_g_0_spanOnDropChannelEn_f;
    field_val = GetMcQWriteSpanOnDropCtl(V, g_0_spanOnDropChannelEn_f + ((src_pp_id << 1) | src_dp_id) * step, &mc_span_ctl);

    drop_monitor->enable = CTC_IS_BIT_SET(field_val, src_dp_chan);
    if(drop_monitor->enable == 0)
    {
        return CTC_E_NONE;
    }
    for (index = 0; index <= 15; index++)
    {
        if (1 == (GetMcQWriteSpanOnDropCtl(V, spanOnDropRandomThreshold_f, &mc_span_ctl) >> (15 - index)))
        {
            drop_monitor->rate = index;
            break;
        }
    }
    drop_monitor->pri_class_bmp = GetMcQWriteSpanOnDropCtl(V, spanOnDropTrafficClass_f, &mc_span_ctl);
    dst_dp_chan = GetMcQWriteSpanOnDropCtl(V, sodDest_channelId_f, &mc_span_ctl);
    dst_dp_id = GetMcQWriteSpanOnDropCtl(V, sodDest_dpId_f, &mc_span_ctl);
    dst_pp_id = GetMcQWriteSpanOnDropCtl(V, sodDest_ppId_f, &mc_span_ctl);

    if(SYS_DMA_SUB_CHAN == dst_dp_chan && 0 == dst_dp_id)
    {
        drop_monitor->dst_gport = 0x10000000;
    }
    else
    {
        dst_chan_val = (dst_pp_id << 6) | (dst_dp_id << 5) | dst_dp_chan;
        CTC_ERROR_RETURN(sys_usw_get_gchip_id(lchip, &gchip));
        for (lport = 0; lport < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); lport++)
        {
            dmps_port_info.gport = CTC_MAP_LPORT_TO_GPORT(gchip, lport);
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &dst_chan_id));
            if (!SYS_IS_NETWORK_CHANNEL(dst_chan_id))
            {
                continue;
            }
            cmd = DRV_IOR(UcQWritePortChannelMap_t, UcQWritePortChannelMap_g_0_channelId_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, dst_chan_id, cmd, &field_val));
            if (dst_chan_val == field_val)
            {
                break;
            }
        }
        drop_monitor->dst_gport = dmps_port_info.gport;
    }

    return CTC_E_NONE;
}

int32
sys_at_set_monitor_drop_discard(uint8 lchip, uint8 enable)
{
    EpeHdrAdjSpanCtl_m hdradj_span_ctl;
    McQWriteSpanOnDropCtl_m mc_span_ctl;
    EpeHdrAdjExcp_m epe_hdr_excp;
    sys_port_info_t port_info;
    uint32 field_val = 0;
    uint32 cmd = 0;
    uint8 pp_id = 0;

    sal_memset(&epe_hdr_excp, 0, sizeof(EpeHdrAdjExcp_m));
    sal_memset(&hdradj_span_ctl, 0, sizeof(EpeHdrAdjSpanCtl_m));
    sal_memset(&mc_span_ctl, 0, sizeof(McQWriteSpanOnDropCtl_m));
    sal_memset(&port_info, 0, sizeof(sys_port_info_t));

    cmd = DRV_IOR(EpeHdrAdjExcp_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &epe_hdr_excp));/*uc*/
    field_val = GetEpeHdrAdjExcp(V, discardEn_f, &epe_hdr_excp);

    if(field_val == !!enable)
    {
        return CTC_E_NONE;
    }

    cmd = DRV_IOR(McQWriteSpanOnDropCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &mc_span_ctl));
    if (!enable && p_usw_queue_master[lchip]->monitor_drop_en)
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, MCHIP_CAP(SYS_CAP_RSV_PORT_MOD_ID), 0, &port_info));
        if(port_info.chan_id != SYS_COMMON_USELESS_CHANNEL
            && port_info.sub_chan_id == GetMcQWriteSpanOnDropCtl(V, sodDest_channelId_f, &mc_span_ctl)
            && port_info.pp_id == GetMcQWriteSpanOnDropCtl(V, sodDest_ppId_f, &mc_span_ctl)
            && port_info.dp_id == GetMcQWriteSpanOnDropCtl(V, sodDest_dpId_f, &mc_span_ctl))
        {
            SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Can Not Disable Queue_Drop_En When Span On Drop Dst Port is MOD Port. \n");
            return CTC_E_INVALID_CONFIG;
        }
    }

    field_val = !!enable;
    lchip = SYS_PP_BASE(lchip);
    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        cmd = DRV_IOR(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl));
        SetEpeHdrAdjSpanCtl(V, spanOnDropDiscardEn_f, &hdradj_span_ctl, field_val);/*mc*/
        SetEpeHdrAdjSpanCtl(V, spanOnDropSpanPktUnset_f, &hdradj_span_ctl, field_val);
        cmd = DRV_IOW(EpeHdrAdjSpanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip + pp_id, 0, DRV_CMD_PP_EN(cmd), &hdradj_span_ctl));
    }

    SetEpeHdrAdjExcp(V, discardEn_f, &epe_hdr_excp, field_val);
    SetEpeHdrAdjExcp(V, isSpanPkt_f, &epe_hdr_excp, !field_val);
    cmd = DRV_IOW(EpeHdrAdjExcp_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, MCHIP_CAP(SYS_CAP_MONITOR_ON_DROP_SPAN_INDEX) << 3, cmd, &epe_hdr_excp));/*uc*/

    return CTC_E_NONE;
}

int32
sys_at_qos_set_global_config(uint8 lchip, ctc_qos_glb_cfg_t* p_glb_cfg, sys_nh_info_dsnh_t* p_nhinfo)
{
    int32 ret = CTC_E_NONE;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    switch (p_glb_cfg->cfg_type)
    {
    case CTC_QOS_GLB_CFG_RESRC_MGR_EN:
        ret = sys_at_qos_resrc_mgr_en(lchip, p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_SHAPE_PKT_EN:
        ret = sys_at_qos_set_glb_port_shp_base_pkt_en(lchip, p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_REASON_SHAPE_PKT_EN:
        if (0 == p_glb_cfg->u.value)
        {
            /*for arctic, dma queue not support bps mode*/
            return CTC_E_NOT_SUPPORT;
        }
        break;
    case CTC_QOS_GLB_CFG_QUEUE_DROP_MONITOR_EN:
        ret = sys_at_qos_set_monitor_drop_queue_id(lchip, &p_glb_cfg->u.drop_monitor, p_nhinfo);
        break;
    case CTC_QOS_GLB_CFG_SCH_WRR_EN:
        ret = sys_at_qos_set_glb_wrr_enable(lchip, p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_FCDL_ACTION:
        ret = sys_at_qos_set_fcdl_action(lchip, p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_FCDL_INTERVAL:
        ret = sys_at_qos_set_fcdl_interval(lchip, p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_ROUND_TRIP_MODE:
        ret = sys_at_qos_set_round_trip_mode(lchip, p_glb_cfg->u.value);
        break;
    default:
        ret = CTC_E_NOT_SUPPORT;
        break;
    }

    return ret;
}

int32
sys_at_qos_get_global_config(uint8 lchip, ctc_qos_glb_cfg_t* p_glb_cfg)
{
    int32 ret = CTC_E_NONE;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    switch (p_glb_cfg->cfg_type)
    {
    case CTC_QOS_GLB_CFG_QUEUE_DROP_MONITOR_EN:
        ret = sys_at_qos_get_monitor_drop_queue_id(lchip, &p_glb_cfg->u.drop_monitor);
        break;
    case CTC_QOS_GLB_CFG_FCDL_ACTION:
        ret = sys_usw_qos_get_fcdl_action(lchip, &p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_FCDL_INTERVAL:
        ret = sys_at_qos_get_fcdl_interval(lchip, &p_glb_cfg->u.value);
        break;
    case CTC_QOS_GLB_CFG_ROUND_TRIP_MODE:
        ret = sys_at_qos_get_round_trip_mode(lchip, &p_glb_cfg->u.value);
        break;
    default:
        ret = CTC_E_NOT_SUPPORT;
        break;
    }
    return ret;
}


int32
sys_at_qos_init(uint8 lchip, void* p_glb_parm)
{
    int32 ret = CTC_E_NONE;
    uint8 pp_id = 0;
    uint8 pp_base = 0;
    if (NULL != p_usw_queue_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_INIT_GLOBAL(lchip, p_usw_queue_master);

    p_usw_queue_master[lchip] = mem_malloc(MEM_QUEUE_MODULE, sizeof(sys_queue_master_t));
    if (NULL == p_usw_queue_master[lchip])
    {
        return CTC_E_NO_MEMORY;
    }
    sal_memset(p_usw_queue_master[lchip], 0, sizeof(sys_queue_master_t));

    CTC_ERROR_GOTO(sys_usw_qos_class_init(lchip), ret, error0);
    CTC_ERROR_GOTO(sys_usw_qos_policer_init(lchip, p_glb_parm), ret, error1);
    CTC_ERROR_GOTO(sys_at_queue_enq_init(lchip, p_glb_parm), ret, error2);
    CTC_ERROR_GOTO(sys_at_queue_sch_init(lchip), ret, error3);
    CTC_ERROR_GOTO(sys_at_queue_shape_init(lchip), ret, error4);
    CTC_ERROR_GOTO(sys_at_queue_drop_init(lchip, p_glb_parm), ret, error5);
    CTC_ERROR_GOTO(sys_usw_queue_cpu_reason_init(lchip), ret, error6);

    pp_base = SYS_PP_BASE(lchip);
    /* init multi PP module */
    for (pp_id = 1; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        p_usw_queue_master[pp_base + pp_id] = p_usw_queue_master[pp_base];
        CTC_ERROR_GOTO(sys_usw_qos_policer_init(pp_base + pp_id, p_glb_parm), ret, error7);
    }
    return CTC_E_NONE;

error7:
    for (pp_id = 1; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        sys_usw_qos_policer_deinit(lchip + pp_id);
    }
error6:
    sys_at_queue_drop_deinit(lchip);
error5:
    sys_at_queue_shape_deinit(lchip);
error4:
    sys_at_queue_sch_deinit(lchip);
error3:
    sys_at_queue_enq_deinit(lchip);
error2:
    sys_usw_qos_policer_deinit(lchip);
error1:
    sys_usw_qos_class_deinit(lchip);
error0:
    mem_free(p_usw_queue_master[lchip]);
    return ret;
}

int32
sys_at_qos_deinit(uint8 lchip)
{
    uint8 pp_id = 0;
    uint8 pp_base = 0;
    if (NULL == p_usw_queue_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_DEINIT_GLOBAL(lchip, p_usw_queue_master);
    sys_usw_queue_cpu_reason_deinit(lchip);

    sys_at_queue_drop_deinit(lchip);

    sys_at_queue_sch_deinit(lchip);

    sys_at_queue_shape_deinit(lchip);

    sys_at_queue_enq_deinit(lchip);

    for (pp_id = 0; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        sys_usw_qos_policer_deinit(lchip + pp_id);
    }

    sys_usw_qos_class_deinit(lchip);
    mem_free(p_usw_queue_master[lchip]);

    /*last step*/
    pp_base = SYS_PP_BASE(lchip);
    for (pp_id = 1; pp_id < SYS_PP_NUM(lchip); pp_id++)
    {
        p_usw_queue_master[pp_base + pp_id] = NULL;
    }
    return CTC_E_NONE;
}

int32
sys_at_qos_api_cb_register(uint8 lchip, void** api_cb)
{
    CTC_PTR_VALID_CHECK(api_cb);

    api_cb[SYS_QOS_API_INIT] = sys_at_qos_init;
    api_cb[SYS_QOS_API_DEINIT] = sys_at_qos_deinit;

    api_cb[SYS_QOS_API_GET_CHAN_BY_PORT] = sys_at_get_channel_by_port;
    api_cb[SYS_QOS_API_ADD_PORT_TO_CHAN] = sys_at_add_port_to_channel;
    api_cb[SYS_QOS_API_REMOVE_PORT_FROM_CHAN] = sys_at_remove_port_from_channel;
    api_cb[SYS_QOS_API_QUE_SET_PORT_DROP_EN] = sys_at_queue_set_port_drop_en;
    api_cb[SYS_QOS_API_SET_DMA_CHAN_DROP_EN] = sys_at_set_dma_channel_drop_en;
    api_cb[SYS_QOS_API_QUE_GET_PORT_DEPTH] = sys_at_queue_get_port_depth;
    api_cb[SYS_QOS_API_SET_FC_DEFAULT_PROFILE] = sys_at_qos_set_fc_default_profile;
    api_cb[SYS_QOS_API_QUE_GET_QUE_ID] = sys_at_queue_get_queue_id;
    api_cb[SYS_QOS_API_GET_CHAN_BY_QUE_ID] = sys_at_queue_get_channel_by_queue_id;
    api_cb[SYS_QOS_API_QUE_DUMP] = sys_at_qos_queue_dump;
    api_cb[SYS_QOS_API_PORT_DUMP] = sys_at_qos_port_dump;
    api_cb[SYS_QOS_API_DUMP_STATUS] = _sys_at_qos_dump_status;
    api_cb[SYS_QOS_API_SET_SHAPE] = sys_at_qos_set_shape;
    api_cb[SYS_QOS_API_GET_SHAPE] = sys_at_qos_get_shape;
    api_cb[SYS_QOS_API_SET_SCHED] = sys_at_qos_set_sched;
    api_cb[SYS_QOS_API_GET_SCHED] = sys_at_qos_get_sched;
    api_cb[SYS_QOS_API_SET_GLB_CFG] = sys_at_qos_set_global_config;
    api_cb[SYS_QOS_API_GET_GLB_CFG] = sys_at_qos_get_global_config;
    api_cb[SYS_QOS_API_SET_QUE] = sys_at_qos_queue_set;
    api_cb[SYS_QOS_API_GET_QUE] = sys_at_qos_queue_get;
    api_cb[SYS_QOS_API_SET_DROP] = sys_at_queue_set_drop;
    api_cb[SYS_QOS_API_GET_DROP] = sys_at_queue_get_drop;
    api_cb[SYS_QOS_API_SET_RESRC] = sys_at_queue_set_resrc;
    api_cb[SYS_QOS_API_GET_RESRC] = sys_at_queue_get_resrc;
    api_cb[SYS_QOS_API_QUERY_POOL_STATS] = sys_at_queue_query_pool_stats;
    api_cb[SYS_QOS_API_QUERY_QUE_STATS] = sys_at_queue_stats_query;
    api_cb[SYS_QOS_API_CLEAR_QUE_STATS] = sys_at_queue_stats_clear;
    api_cb[SYS_QOS_API_GET_CHAN_BY_SUB_CHAN] = sys_at_get_channel_by_sub_channel;
    api_cb[SYS_QOS_API_QUERY_STATS] = sys_at_stats_query;
    api_cb[SYS_QOS_API_CLEAR_STATS] = sys_at_stats_clear;
    api_cb[SYS_QOS_API_SET_EGS_RESRC_GUARANTEE] = sys_at_queue_set_egs_resrc_guarantee;
    api_cb[SYS_QOS_API_TRAVERSE_QUEUE_NODE] = sys_at_queue_traverse_queue_node;
    api_cb[SYS_QOS_API_SET_PORT_DYNAMIC_SWITCH] = sys_at_qos_set_port_dynamic_switch;
    api_cb[SYS_QOS_API_SET_MONITOR_DROP_DISCARD] = sys_at_set_monitor_drop_discard;

    return CTC_E_NONE;
}

#endif

